ATM switching system and cell control method

ABSTRACT

An ATM switching system includes PVC allocation circuits  13 -i corresponding to output queues  14 -i is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has a room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are “input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The application relates to U.S. application Ser. No. 07/845,668filed on Mar. 4, 1992 entitled “ATM Cell Switching System” by T. KOSAKIet al.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to an ATM switching system used forbroadband ISDN, or more in particular to an ATM switching systemsuitably used for burst data communication service carried out inPermanent Virtual Connection (PVC) mode.

[0003] The communication service of the broadband ISDN is either of twomodes; Switched Virtual Connection (SVC) and PVC.

[0004] In SVC mode, Virtual Path Identifier (VPI)/Virtual ChannelIdentifier (VCI) is assigned to a call in the ATM switching system atthe time of setting (connecting) the particular call to establish arouting path while at the same time securing a bandwidth of theparticular call. As a result, in SVC mode, the amount of incoming cellsfor each output line of the ATM switch is accommodated in apredetermined bandwidth, and therefore the storage capacity of theoutput cell buffer provided for each output line can be comparativelysmall.

[0005] In PVC mode, by contrast, VPI/VCI is assigned fixedly betweenspecific communication terminals so that the terminal equipment cancommunicate on a dedicated line whenever required. When thecommunication is in PVC mode, the bandwidth is not secured for theVPI/VCI unlike in the ATM switching system in SVC mode. In the casewhere a plurality of burst data in PVC mode directed to the same outputline are applied at the same time to the ATM switch, therefore,excessive ATM cells beyond the bandwidth of the output line flow intothe buffer memory associated with the output line, and the excess cellsbeyond the buffer capacity are unavoidably discarded.

[0006] The cell discarding can be avoided by two methods. In a method, asufficient buffer capacity is provided to accommodate a plurality ofburst data generated for the same output port. The other method is suchthat the required bandwidth is secured in each system on the data routeeach time before transmission of the burst data from the PVC modeterminal.

[0007] The burst data produced from the PAM or the hard disc of theterminal equipment may amount to as large as 1 Mbits to 1 Gbits. Themethod in which a buffer capacity sufficient to accommodate a pluralityof burst data is secured in the ATM switch involves a vast amount ofbuffer memory capacity, and therefore is not of practical value from theviewpoint of memory utilization.

[0008] In the method in which a bandwidth is secured each time of burstdata transmission in PVC mode, by contrast, the time required forsecuring the bandwidth is not negligible, and the problem is posed of areduced communication efficiency of the terminal equipment. 3

[0009] Assuming that an ATM switching system is employed in whichcontrol information including call control and bandwidth control aregathered in a processor and various control operations are performed sin compliance with commands from the processor. In the case where abroadband ISDN is configured which is capable of transferring data ofabout 10 Mbits at the bit rate of 150 Mb/s within 100 ms, for example,the time required for securing a bandwidth exceeds the time required fordata transfer, so that the overhead time for securing a bandwidth maypose a bottleneck to the burst data communication. This overhead timecan be reduced to some degree by improving the processor capacity. Thisimprovement based on the processor capacity, however, has its own limit.

[0010] There have been proposed various conventional techniques, such asU.S. Pat. No. 5,124,977 and U.S. Pat. No. 5,184,346 both related to aswitching system using a common buffer memory, U.S. Pat. No. 5,099,475related to a switching system in which a high speed line is connected tothe input and output links of an ATM switch through a cell multiplexeror cell demultiplexer, and U.S. Pat. No. 5,280,475 related to trafficshaping method and circuit in which a list structure is formed at everyvirtual path in a common buffer memory to control the reading of cellsby a band control table.

SUMMARY OF THE INVENTION

[0011] An object of the invention is to provide an ATM switching systemand an ATM cell control method which are improved in a way suitable forburst data communication.

[0012] Another object of the invention is to provide an ATM switchingsystem and an ATM cell control method in which a buffer memory ofcomparatively small capacity can be used for each output line, and theburst data in PVC mode can be communicated efficiently.

[0013] In order to achieve the above-mentioned objects, according to theinvention, there are provided an ATM switching system and an ATM cellcontrol method, wherein in the case where a plurality of burst datadirected to the same output line flow into the switching system in atemporally overlapped fashion. Only those cells associated with one or aplurality of burst data specified with the arrival of the leading cellthereof are admitted, while the cells belonging to the other burst dataare discarded.

[0014] Cell admission or discarding is determined in the followingmanner. All the cells associated with burst data with the leading cellthereof arriving when the bandwidth of the output line has room areadmitted, whereas the cells of burst data with the leading cell thereofarriving when there is no room in the bandwidth are all discarded.

[0015] More specifically, in the system according to the invention,state information is stored indicating the state of use of the outputbandwidth of each output line or the use thereof by other burst data. Atthe time point of arrival of the leading cell of each burst data, partof the header information of the leading cell is registered asidentification information for admitted burst data and the leading cellof the admitted burst data is stored temporarily in a buffer memory, ifthe transmission of the particular burst data can be permitted accordingto the state information. In the case where the bandwidth of the outputline is in a state that cannot permit transmission of the burst data atthe time point of arrival of the leading cell, on the other hand, theparticular leading cell is discarded.

[0016] When a cell other than the leading cell of a burst data hasarrived, a decision is made as to whether it should be admitted ordiscarded according to whether the header of the cell contains the burstidentification information registered as described above. Theregistration of the identification information of an admitted burst datais cancelled when the last cell of the particular burst data isprocessed.

[0017] The identification information used for an admitted burst datainclude the identification information contained in the header of theleading cell of the burst data, such as VCI (Virtual ChannelIdentifier), VPI (Virtual Path Identifier), a combined value of VPI andVCI, part of VPI, part of VCI or part of the combined value of VPI andVCI.

[0018] According to one aspect of the invention, in the case where aplurality of burst data directed to the same output port have arrived intemporally overlapped s fashion, whether the burst data is admitted ornot is determined at the time of arrival of the leading cell of theburst data. When a burst data is rejected, the subsequently-arrivingcells of the particular burst data are all discarded, while all thecells of an admitted burst data arriving subsequently are admitted. As aresult, the cell discarding operation caused by congestion is preventedfrom affecting all the burst data, thereby reducing the number of burstdata which are required to be retransmitted due to the cell discarding.

[0019] According to another aspect of the invention, all thesubsequently-arriving cells of a burst data which is rejected arediscarded, and therefore the capacity of the buffer memory required fortemporarily storing the output cells for each output line can bereduced.

[0020] The foregoing and other objects, advantages, manner of operationand novel features of the present invention will be understood from thefollowing detailed description when read in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a diagram showing an example of the generalconfiguration of an ATM switching system according to the presentinvention.

[0022]FIG. 2 is a diagram showing the controller for an ATM switchingsystem shown in FIG. 1 according to an embodiment of the invention.

[0023]FIG. 3 is a diagram showing an ATM switch having the function ofPVC allocation according to an embodiment.

[0024]FIG. 4 is a diagram showing an example of the format of theinternal cell.

[0025]FIG. 5 is a diagram showing a PVC allocation circuit shown in FIG.3 according to an embodiment.

[0026]FIG. 6 is a diagram showing an ATM switch having the PVCallocation function according to another embodiment.

[0027]FIG. 7 is a diagram showing an ATM switch having the PVCallocation function according to still another embodiment.

[0028]FIG. 8 is a diagram showing the buffer controller shown in FIG. 7according to an embodiment.

[0029]FIG. 9 is a diagram showing the PVC allocation circuit shown inFIG. 8 according to an embodiment.

[0030]FIG. 10 is a diagram showing the PVC allocation circuit shown inFIG. 3 or 6 according to another embodiment.

[0031]FIG. 11 is a diagram showing a line interface shown in FIG. 1according to an embodiment.

[0032]FIG. 12 is a diagram showing the header conversion circuit shownin FIG. 11 according to an embodiment.

[0033]FIG. 13 is a diagram of bandwidth control table shown in FIG. 8according to an embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034]FIG. 1 shows an example of the general configuration of an ATMswitching system or an ATM exchanger according to the invention.

[0035] In FIG. 1, reference character L1-i (i=1 to N) designates inputlines, and L6-i (i=1 to N) output lines. These lines transferfixed-length packets (ATM cells) in the form of optical or electricalsignal. The lines L1-i and L6-i are paired to make up a subscriber line(or a trunk line connected to another switching system) connected toterminal equipment. Numeral 1 designates a switch, numeral 2-i (i=1 toN) a channel interface provided for each subscriber line, and numeral 3a controller connected to the switch 1 through lines L3 and L4 on theone hand and to each line interface and the switch 1 through a controlbus L0 on the other hand.

[0036] The cells input from the input lines L1-l to L1-N are subjectedto such processes as opto-electrical conversion, transmission frametermination, cell synchronization according to the system configuration,header conversion and addition of the routing information added asrequired by the switch 1 at the channel interfaces 2-1 to 2-Nrespectively.

[0037] The cells input from the line interface 2-i to the switch 1through line L2-i are distributed among the lines L5-1 to L5-N and L4according to the routing information added to the respective headers.The cells output to the lines L5-1 to L5-N, after being subjected to theprocesses including cell synchronization, transmission frame terminationand electro-optical conversion at the line interfaces 2-1 to 2-N, areoutput to output lines L6-1 to L6-N respectively.

[0038] The switch 1 distributes cells for call process control ornetwork management (hereinafter referred to as the control cells) to theline L4 and transfers them to the controller 3.

[0039] The controller 3 controls the switch 1 and the line interfaces2-1 to 2-N through a control bus L0, while at the same time collectinginformation on these elements through the control bus L0. The controlcircuit 3 generates cells including control information to betransmitted to the terminal equipment connected to the subscriber lineor other ATM switching systems and output it to the line L3. These cellsare distributed to the lines L5-1 to L5-N by the switch 1, andtransferred through the line interfaces to the destination terminalequipment or another ATM switching system.

[0040]FIG. 2 shows the controller 3 according to an embodiment.

[0041] The controller 3 includes a signaling circuit 30, a controlprocessor 31 and a memory 32.

[0042] The control cells input from the line L4 are assembled into amessage at the signalling circuit 30 and applied through the control busL0 to the control processor 31.

[0043] The control processor 31 decodes the contents of the messagereceived from the signalling circuit 30, stores necessary information inthe memory 32, and issues an instruction to the control bus L0 forcontrolling the switch 1 and the line interfaces 2-1 to 2-N as required.

[0044] Also, the message including the control information destined foranother ATM switching system or terminal equipment generated at thecontrol processor 31 is separated into cells at the signalling circuit30 and output to the line L3.

[0045]FIG. 3 is a diagram for explaining the basic configuration andoperation of the ATM switch according to the invention.

[0046] The ATM switch 1 includes a multiplexer 1, a plurality of queuefilters 12-i (i=1 to N), PVC allocation circuits 13-i (i=1 to N) andFIFO buffers 14-i (i=1 to N) associated with the output lines L5-1 toL5-N) respectively.

[0047] Cells input in parallel from the lines L2-1 to L2-N are convertedinto a serial string of cells at the multiplexer 11, and then applied tothe queue filters 12-i to 12-N in parallel.

[0048] Each queue filter 12-i decides whether the cell input thereto isthe one to be output to the output line L5-i corresponding to theparticular queue filter on the basis of the routing information of theinput cell, and applies only the cells to be so output to the PVCallocation circuit 13-i selectively.

[0049] The PVC allocation circuits 13-i perform burst cell controloperation corresponding to the valid bandwidth of the output linesdescribed later, and supply the input cells selectively to the FIFObuffers 14-i.

[0050] The cells stored in the FIFO buffers 14-i are read out to theoutput lines L5-i in accordance with the output line speed.

[0051] The switch 1 is capable of accommodating two types of servicesincluding SVC (Switched Virtual Connection) mode and PVC (PermanentVirtual Connection) mode.

[0052] The SVC mode is for securing the bandwidth on the output lineL5-i of the switch 1 at the time of call connection and sets a call insuch a manner as not to exceed the bandwidth of the particular outputline. In this case, even it cells are input concentratively to the sameoutput port from a plurality of ones of the input lines L2-1 to L2-N, itis a temporary phenomenon. The bandwidth, therefore, does not exceed thechannel speed of the output lines L5-1 to L5-N. As a result, as far asthe capacity of the FIFO buffers 14-1 to 14-N is sufficient, theprobability that the cells overflow the buffer is reduced considerably,thereby eliminating the need of adjustment of cell flow rate by the PVCallocation circuits 13-1 to 13-N.

[0053] The PVC mode, on the other hand, is a communication servicesuitable for transferring burst data which are generated more frequentlyand sporadically than in the circuit switching. In PVC mode, in order toprevent the frequency of call control and time waste of call control,calls are normally fixedly assigned to the transmit and receiveterminals. In this way, the call control by the controller 3 isconserved at the time of burst data transmission. The PVC mode assumesthe fact that transmission of each burst data is instantaneous and thata plurality of burst data transmissions rarely compete on the same line.The bandwidth allocation to the output lines corresponding to calls istherefore omitted.

[0054] The problem of the PVC service is that as shown in FIG. 3, forexample, in the case where burst data are input in temporally overlappedfashion from a plurality of input lines L2-1 to L2-N, i.e., in the casewhere a plurality of continuous cell strings are directed toward thesame output line, say, L5-l, the amount of cells input to the FIFObuffer 14-1 of the output line exceeds the output bandwidth.

[0055] Generally, the capacity of the FIFO buffers 14-1 to 14-N isdesigned on the assumption that the amount of cells applied thereto iswithin the bandwidth of the respective output lines. The FIFO buffers14-1 to 14-N, therefore, are not always capable of accommodating theamount of cells beyond the bandwidth flowing in continuously for apredetermined period of time as when a plurality of burst data aregenerated concurrently as mentioned above.

[0056] When cells exceeding the output bandwidth flow in, theFIFO-buffers are filled up so that subsequently arriving cells overflowthe buffers and are discarded. In the process, all the burst data havepart of subsequently-arriving cells thereof discarded, and therefore allof a plurality of competing burst data remain incomplete makingretransmission inevitable.

[0057] In view of the above-mentioned phenomenon, according to theinvention, discarding of cells for at least one of the competing burstdata is avoided to permit data transfer in complete form. For thispurpose, the invention includes PVC allocation circuits 13-i (i=1 to N)for selectively controlling the cell input to the FIFO buffers.

[0058] According to the invention, with the arrival of the leading cellof burst data in PVC mode, if the output buffer haa a sufficient room ofbandwidth, the PVC allocation circuit 13 registers the identifier (PVC)of the burst data as identification information of the admitted burst sothat the leading cell and the subsequently-arriving burst data cellshaving the registered identification information are stored (admitted)in the output buffer.

[0059] In the event that the bandwidth of the output buffer has nosufficient room at the time of arrival of the leading cell, by contrast,the PVC is not registered and the leading cell is discarded (not storedin the buffer), so that the subsequently arriving burst data cellshaving unregistered identifiers are also discarded.

[0060] According to a simplest embodiment of the invention, assumingthat a plurality of burst data compete on the same output line. Each PVCallocation circuit admits only the first burst data to pass through anddiscard all the cells of subsequently-arriving burst data until thefirst burst data has passed out. In this case, the PVC registered asadmitted burst identification information at the time of arrival of theleading cell of the first burst data is deleted from registration whenthe last cell of the particular burst data arrives. Until this PVCregistration is deleted, PVC of other burst data is not registered. Allthe cells of the subsequently-arriving burst data having no admittedburst identification information are thus discarded, while the burstdata with the leading cell thereof arriving first after PVC deletion isadmitted anew.

[0061] In the case of FIG. 3, two burst data arrive at the input linesL2-1 and L2-N at the same time. The burst data on line L2-1 whoseleading cell arrives earlier, however, acquires the right of way, sothat the PVC allocation circuit 13-1 admits the burst data cell on lineL2-1 and discards all the burst data cells on the line L2-N.

[0062] According to this embodiment, all cells of the first-arrivingburst data on line L2-1 are admitted in the FIFO buffer in competition,and the particular burst data is transferred in complete form. Thus theonly burst data on line L2-N is required to be retransmitted.

[0063]FIG. 4 shows an example of cell format input to the switch of FIG.3.

[0064] The input cell includes a header 400 and an information section410. The header 400 includes a validity indication field 401 indicatingwhether the cell is valid or not, a start indication field 402indicating that the cell is the leading one of the data (burst data), anend indication field 403 indicating that the cell is the last one of thedata (burst data), a field 404 indicating the output line (output queue)providing routing information, and a VPI/VCI (PVC) field providing callidentification information.

[0065] The switch decides which of the queue filters 12-1 to 12-N is tobe supplied with the input cell according to the output queue number 404of the header information of the cell.

[0066] In the case where the information indicating the start (leadingcell) is set in the field 402, the PVC allocation circuits 13-1 to 13-Nstore (register) in the associated buffer the PVC value contained in thefield 405 of the cell as identification information of the admittedburst data unless the buffer is occupied by other burst data.

[0067] The PVC value used for this purpose is the VCI value, the VPIvalue, an integrated value of VPI and VCI, or part of these values setin the field 405.

[0068] In the case where a cell other than the leading cells of theburst data is input, the PVC allocation circuits 13-1 to 13-N decidewhether the field 405 of the cell contains the same identificationinformation as the admitted burst data registered at the time of arrivalof the leading cell thereof. Only those cells which coincide with theidentification information in registration are admitted and theremaining cells are discarded.

[0069] With the arrival of a cell containing the end indication (lastcell indication) in the field 403, if this cell is the last cell ofadmitted burst data, the PVC allocation circuits 13-1 to 13-N cancel theregistration of the identification information of the admitted burstdata and are ready to admit other burst data whose leading cellssubsequently arrive in the output buffer.

[0070]FIG. 5 is a diagram showing the PVC allocation circuit 13-iaccording to an embodiment in FIG. 3.

[0071] A header analysis circuit 131 separates and outputs the validityindication field 401, the start indication field 402, the end indicationfield 403 and the PVC field 405 of the input cell.

[0072] In the case where the validity indication field contains thevalue “0” indicating an idle cell, an AND circuit 13 d outputs a signal“0” and causes a selector 13 e to selectively output an idle cellpattern.

[0073] A used/unused register 138 is for storing information as towhether an output line is busy for transmission of burst data(information indicating whether the output line has a room ofbandwidth). The PVC register 139 stores the PVC (identificationinformation on the admitted burst data) of the burst data currentlyusing the output line.

[0074] The PVC/SVC register 13 a indicates whether the queue processedby the PVC allocation circuit is associated with SVC mode or PVC mode.

[0075] Assuming that the register is set in SVC mode, the PVC/SVCregister 13 a outputs a signal “1”, causes an OR circuit 13 c to outputa “1” signal, causes an AND circuit 13 d to output a signal “1” when thevalidity indication field is “1” indicating a valid cell, and causes aselector 13 e to pass the input cell as it is. In this case, the PVCallocation circuit does not manage the burst data but passes cellsfreely.

[0076] In the case where the PVC/SVC register 13 a is set in PVC mode,in contrast, the OR circuit 13 c does not output a signal “1” unless theoutput of the AND circuit 133 or 135 is “1”. As a result, under thiscondition, the cell output is controlled by the output of the ANDcircuit 133 or 135.

[0077] The PVC/SVC register 13 a is set to a given mode by thecontroller 3 through a control bus L0 and a microcomputer interfacecircuit 13 b.

[0078] The PVC/SVC register 13 a of each output line is set to SVC modeas initial state, for example, and when PVC service is requested for aspecific output line, the associated PVC/SVC register 13 a is switchedto PVC mode.

[0079] Next, detailed explanation will be made about the operation inthe case where the PVC/SVC register 13 a indicates PVC mode.

[0080] When an input cell indicates a leading cell, the used/unusedregister 138 outputs a signal “0” indicating that it is busy. When thevalidity indication field of the input cell is “1” indicating a validcell, the AND circuit 133 outputs a signal “1”.

[0081] In the process, on condition that the AND circuit 134 outputs “0”(when the last cell is not involved), the AND circuit 136 outputs “1”,and the OR circuit 137 sets the load input LD of the register 138 to“1”, thereby setting the used/unused register 138 to “1” indicating thatit is busy. Also, the PVC value output from the header analysis circuit131 is set in the PVC register 139. Further, the output “1” of the ANDcircuit 133 causes the selector 13 e to output an input cell selectivelythrough the OR circuit 13 c and the AND circuit 13 d. This operationpermits the PVC to be registered at the time of arrival of the leadingcell of the burst data.

[0082] Assuming that when the input cell is in start indication, theused/unused register 138 indicates that the burst data is busy withburst data registration. The output of the used/unused register 138 is“1”, and that of the AND circuit 133 “0”. Therefore, no value is set inthe used/unused register 138. In this case, the input cell is notsubjected to selective output control through the OR circuit 13 c.

[0083] This operation indicates that if the buffer is being used by apreviously-arriving burst data at the time of arrival of the leadingcell of another burst data, the PVC registration of the second-arrivingburst data is impossible.

[0084] Assuming that an input cell is the last cell (with the field 403indicating the presence of end indication). The validity indicationfield 401 is “1” indicating the presence of a valid cell, and theused/unused register 138 output a signal “1” indicating that it is busy.Also, the AND circuit 134 outputs a signal “1” when a matching detectioncircuit 132 outputs “1” indicating that the PVC registered in the PVCregister 139 coincides with the PVC of the output from the headeranalysis circuit 131.

[0085] Under this condition, the AND circuit 136 outputs a signal “0”,and the OR circuit 137 “1”. The used/unused register 138 is thus set to“0” indicating the idle state. As a result, the buffer is usable byanother new burst data which may arrive.

[0086] In the case where an input cell is valid with the used/unusedregister 138 indicating the busy state and the value of the PVC register139 coincides with that of the input cell PVC, then the AND circuit 135outputs “1”. The selector 13 e is thus caused to selectively output theinput cell through the OR circuit 13 c and the AND circuit 13 d. Thiscontrol process makes it possible to admit the PVC cell in use which mayarrive.

[0087]FIG. 3 shows the case in which only one burst data is admitted ata time on a single output line. In the case where the maximum bandwidthof the burst data is 10 Mb/s and the bandwidth of the output line 150Mb/s, however, 15 burst data can be admitted at a time on a singleoutput line.

[0088]FIG. 6 shows an example of the ATM switch configuration in which aplurality of burst data can be admitted on a single output line.

[0089] In this example, a single output line such as L15-i is associatedwith a plurality of queue filters 12-11 to 12-lm, a plurality of PVCallocation circuits 13-11 to 13-lm, a plurality of FIFO buffers 14-11 to14-lm, a single selector 15-1 and a bandwidth control table 16-1connected to the selector 15-1.

[0090] Each PVC allocation circuit can pass only one burst data at atime. Since a plurality of PVC allocation circuits are available foreach output line, however, up to a number m of burst data can beadmitted at a time on each output line.

[0091] A bandwidth control table 16-1 outputs a queue number (FIFObuffer number) corresponding to the timing signal output from an outputtiming counter 17, and causes the selector 15-1 to select one of theFIFO buffers 14-11 to 14-lm corresponding to the particular queuenumber.

[0092] In this configuration, assuming that a specified PVC allocationcircuit 13-11 alone is set to SVC mode and the other PVC allocationcircuits 13-12 to 13-lm to PVC mode. The FIFO buffer 14-11 connected tothe specific PVC allocation circuit 13-11 is supplied with cellsdedicated for SVC mode. The cells are output in a bandwidth assigned onthe bandwidth control table 16-1, and the remaining bandwidth can beassigned to the number m-1 of burst data. In this way, cells fordifferent service calls can be admitted on a single output line.

[0093] Although the case of FIG. 6 shows the configuration in which aplurality of physically separated queues are provided on each outputline, the configuration with a multiplicity of queues provided onstand-alone basis is accompanied by a large segmentation loss and isdisadvantageous for hardware realization.

[0094] FIGS. 7 to 9 show an example of the switch configuration with ashared or common buffer which is functionally equivalent to that shownin FIG. 6.

[0095] In FIG. 7, the ATM switch comprises a multiplexer 11, a commonbuffer 18, a demultiplexer 19 and a buffer controller 10.

[0096] Cells input in parallel from the input lines L2-1 to L2-N aretime-division multiplexed at a multiplexer 11 and input to the commonbuffer 18 as a serial stream of cells.

[0097] The buffer controller 10 analyzes the header of each cell outputto a signal line L14 from the multiplexer 11, determines the address ofa list structure to which the cell is to be linked, and applies theaddress as a write address to the common buffer.

[0098] Also, the buffer controller 10 gives a read address to the commonbuffer 18 at a predetermined timing in step with the cell output to theoutput lines L5-1 to L5-N and reads the cells out of the common buffer18. The demultiplexer 19 distributes the cells read out of the commonbuffer 18 among the output lines L5-1 to L5-N periodically.

[0099]FIG. 8 is a diagram showing the buffer controller 10 of FIG. 7according to an embodiment.

[0100] The header of an input cell is input to a PVC allocation circuit107 through line L14. The PVC allocation circuit 107 performs thecontrol operation for registering the identifier (PVC allocation) for anadmitted burst data and discarding the cells of the burst data notadmitted. The PVC allocation circuit 107 also outputs an output queuenumber to line L100, and a write enable signal to line L152. As aresult, a write address corresponding to the queue number is read from awrite address memory (WARAM) 101 and output to line L150.

[0101] Numeral 103 designates a next address memory for storing thepointer address (write address or read address) indicating the record(cell data) to be next accessed for each of a plurality of queues formedin a common buffer 18 (FIG. 7).

[0102] In the input cell write cycle, an unused address is output fromthe top of the FIFO 104 providing the address queue storing an idleaddress, and is supplied to the write address memory WARAM 101 and thenext address memory 103 respectively as data (next address). The writeaddress memory WARAM 101 has a plurality of record storage positionscorresponding to the queue numbers.

[0103] Now, the write address memory WARAM 101 is addressed by the queuenumber extracted from the header of the input cell by the PVC allocationcircuit, and the next address stored previously is read out from thememory position corresponding to the queue number. Then, the idleaddress retrieved from the FIFO 104 is stored as the next new address inthe same storage position.

[0104] The next address memory 103 for storing the idle address (nextaddress) is supplied with the previously-stored next address output fromthe write address memory WARAM 101 as a write address WA.

[0105] The write address WA is used also for writing the input cell tothe common buffer 18 shown in FIG. 7. Consequently, pairs of the inputcell and the next address are stored in the common buffer memory 18 andthe next address memory 103 respectively.

[0106] In the case where a cell having the same queue number as thecurrently-stored cell arrives subsequently, assume that the input cellis written into the common buffer 18 with the next address output fromthe write address memory WARAM 101 addressed by the queue number as awrite address WA. Then, the memory position of the particular input cellin the common buffer coincides with the address stored in the nextaddress memory 103 in a pair with the previous input cell. Thus a liststructure is configured in which the cell codes having the same queuenumber are linked successively by the next address stored in the nextaddress memory.

[0107] In the cell read cycle from the common buffer 18, a queue numberto be accessed (read) from the bandwidth control table 105 is output inresponse to the timing supplied from the output timing counter 106.

[0108] A valid cell detector 108 includes a plurality of counter areascorresponding to the queue numbers. At the time of writing cell datainto a common buffer, the count value of the counter area correspondingto the queue number of the input cell is incremented. At the time ofreading the cell data from the common buffer, on the other hand, thecount value of the counter area corresponding to the queue number givenfrom the bandwidth control table is checked to decide whether a cellexists in the corresponding queue in the common buffer.

[0109] The valid cell detector 108, when supplied with the queue numberfor a cell to be read out of line L103, if the cell exists in theparticular queue, outputs a read enable signal and decrements the countvalue.

[0110] Numeral 102 designates a read address memory (RARAM) having aplurality of storage areas for storing the next read addresscorresponding to the queue number and outputting the next read addressfrom the storage area corresponding to the queue number designated fromline L103 when the read enable signal is a “1”.

[0111] The read address output from the memory 102 is applied as a readaddress RA to the common buffer 18 and the next address memory 103through line L1. As a result, one cell data is read from the queuecorresponding to the queue number of the common buffer 18, and insynchronism with it, the next address is read from the next addressmemory 103.

[0112] The next read address is stored in a storage area correspondingto the queue number of the read address memory 102 and provides a readaddress for next accessing the queue of the same queue number.

[0113] The address RA read to line L151 from the read address memory 102becomes useless and is stored as an unused address in an idle addressFIFO 104.

[0114] The bandwidth control table 105, as shown in FIG. 13, forexample, has record areas in the same number as the output lines (outputports) of the switch 1. The read permit/prohibit information and thequeue number information (corresponding to the RARAM address) are storedin the respective record areas.

[0115] When the output port number generated in the output timingcounter 106 shown in FIG. 8 is applied as an address to the bandwidthcontrol table 105, the read enable/inhibit information and the queuenumber information are read from the record area corresponding to theoutput port number. In the case where the read permit/prohibitinformation is in “prohibit” state, no cells are read from the commonbuffer.

[0116] The contents of the records in the bandwidth control table areset by the controller 3 through the control bus L0.

[0117] In the bandwidth control table shown in FIG. 13, assuming thatthe same queue number is set in at least two record areas designated bydifferent output port numbers. Cells can be output to a plurality ofoutput ports of the switch from the same queue, thus making it possibleto output cells at a rate twice or more than from the normal queue.

[0118] Conversely, assuming that the number of records in the bandwidthcontrol table is set to four times the number N of output ports, forexample, that the output timing counter 106 is caused to generate portnumbers 1 to 4N and that the queue number “1” is written only at thefirst address of the bandwidth control table. The cell of the queuenumber “1” is read out on the output port 1 once every four times, andtherefore cells can be output in one-fourth of the bandwidth.

[0119] In this way, the bandwidth control table can control the cellread speed from each queue and thus can control the bandwidth for eachqueue depending on how the contents thereof are set.

[0120]FIG. 9 is a diagram showing the PVC allocation circuit 107 of FIG.8 according to an embodiment.

[0121] A header analysis circuit 131′ extracts the contents of thevalidity indication field, the start indication field, the endindication field, the PVC field and the queue number field from theheader of the input cell. In the case where the signal of the validityindication field is a “0” indicating an idle cell, the AND circuit 13 doutputs a “0” and prohibits the write operation into the common buffer18.

[0122] A used/unused RAM 138′ is for storing information on theused/unused state of the burst data for each queue number, and a PVC RAM139′ is for storing the PVC of the burst data in use for each queuenumber. Also, a PVC/SVC RAM 13 a′ is for designating SVC mode or PVCmode for each queue number.

[0123] When SVC mode is designated, the PVC/SVC RAM 13 a′ outputs a “1”,causes the OR circuit 13 c to output a “1”, causes the AND circuit 13 dto output a “1” indicating the presence of a valid cell as a validityindication, and causes the input cell to be written into the commonbuffer 18. As a result, the PVC allocation circuit 107 does not managethe burst data but performs the cell write operation.

[0124] If the designation is PVC mode, on the other hand, the OR 13 cdoes not output a “1” unless the output of the AND circuit 133 or 135 isa “1”. In this case, therefore, the output of the AND circuit 133 or 135controls the cell write operation. The mode for the PVC/SVC RAM 13 a′ isset from the controller 3 through the control bus L0 and themicrocomputer interface circuit 13 b′.

[0125] Now, explanation will be made about the opera tion in the casewhere the PVC/SVC RAM 13 a′ designates the PVC mode with respect to thequeue number of the input cell.

[0126] When the input cell is the leading cell of the burst data (whenstart indication is given), assuming that the used/unused RAM 138′outputs a “0” indicating s the unused state and that the validityindication is a “1” indicating the presence of a valid cell. Then, theAND circuit 133 outputs a “1”.

[0127] In the process, on condition that-the AND circuit 134 outputs a“0” (the value where the end indication is not set), the AND circuit 136outputs a “1” and the OR circuit 137 sets the data load LD to a “1”. Asa result, a “1” indicating the used state of the record areacorresponding to the queue number of the input cell is set on theused/unused RAM 138′.

[0128] Also, the PVC value output from the header analysis circuit 131′is set in the record area corresponding to the queue number of the inputcell in the PVC RAM 139′. Further, the “1” output from the AND circuit133 causes the AND circuit 13 d to output a cell write enable signalthrough the OR circuit 13 c. This operation permits the PVC to beregistered at the time of arrival of the leading cell of the burst data.

[0129] In the case where an input cell is the leading cell and theused/unused RAM 138′ indicates the used state of the burst data, theoutput of the used/unused RAM 138′ is a “1” and the AND circuit 133outputs a “0”. As a consequence, no value is set in the used/unused RAM138′. Nor is the operation performed for writing the input cell into thecommon buffer 18 through the OR circuit 13 c. In other words, in thecase where the output line is already occupied by another burst data atthe time of arrival of the leading cell of a given burst data, the PVCof the newly-arriving burst data has the identifier thereof notregistered for admission.

[0130] Assuming that an input cell is the last cell (with endindication). The AND circuit 134 outputs a “1” in the case where thevalidity indication is a “1” indicating the presence of a valid cell,the used/unused RAM 138′ outputs a “1” indicating the used state, andthe output of the matching detector 132 is a “1” indicating that the PVCregistered in the PVC RAM 139′ coincides with the PVC of the output ofthe header analysis circuit 131′.

[0131] In the process, the AND circuit 136 outputs a “0”, and the ORcircuit 137 a “1”. Therefore, a “0” indicating the unused state is setin the record area corresponding to the queue number of the input cellin the used/unused RAM 138′. As a result, the output line becomes readyfor use by other burst data that may arrive.

[0132] Assuming that an input cell is a valid cell, the used/unused RAM138′ indicates the used state, and that the value of the PVC RAM 139′coincides with the PVC value of the input cell. The AND circuit 135outputs a “1”, and causes the AND circuit 13 d to output a write enablesignal through the OR circuit 13 c. As a result of this control, a PVCcell in use which may arrive is admitted.

[0133] The PVC allocation circuit shown in FIGS. 5 and 9 is a case inwhich only one burst data is admitted for each queue. An embodiment willbe explained below in which a plurality of burst data are admitted foreach queue.

[0134]FIG. 10 shows a configuration replacing the PVC allocation circuitof FIG. 3 or 6, in which a plurality of burst data can be set for eachqueue.

[0135] The input cell has the validity indication field, the startfield, the end field and the PVC field thereof separated and extractedby a header analysis circuit 131. In the case where the validityindication field signal outputs a “0” indicating an idle cell, the ANDcircuit 13 d outputs a “0” and causes the selector 13 e to output anidle cell pattern.

[0136] A CAM (Content-Addressable Memory) 13 f is a memory forregistering the PVC of the burst data, and an unused address FIFO 13 gis for storing the address not used by the CAM 13 f.

[0137] An up-down counter 13 h is for counting the number of burst datain registration, and a comparator 13 i for deciding whether the numberof burst data in registration has exceeded a predetermined thresholdvalue and holding the number of burst data admitted in each queue belowthe threshold value.

[0138] The PVC/SVC register 13 a is for designating the SVC mode or PVCmode of the queue processed by the PVC allocation circuit. In the casewhere SVC mode is designated, the PVC/SVC register 13 a outputs a “1”,causes the OR circuit 13 c′ to output a “1”, causes the AND circuit 13 dto output a “1” with the validity indication of “1” indicating thepresence of a valid cell, and causes the selector 13 e to admit theinput cell as it is.

[0139] As a result, the PVC allocation circuit passes the cell freelywithout managing the burst data. In the case where the PVC/SVC register13 a designates the PVC mode, on the other hand, the output of the ORcircuit 13 c′ is not a “1” unless the output of the AND circuit 133′ or134′ is a “1”. In this case, the cell output is controlled according tothe output of the AND circuit 133′ or 134′. The mode of the PVC/SVCregister 13 a is set from the controller 3 through the control bus L0and the microcomputer interface circuit 13 b.

[0140] Now, explanation will be made about the control operation withthe PVC mode designated by the PVC/SVC register 13 a.

[0141] The PVC extracted by the header analysis circuit 131 at the timeof cell arrival is input to the CAM 13 f as an address, and the CAM 13 foutputs the result of decision whether admission is registered or notCorresponding to the input PVC. In the case where the admission isregistered, an input cell selection instruction is applied to theselector 13 e through the OR circuit 13 c′ and the AND circuit 13 d.

[0142] Assuming that an input cell is the leading cell of the burst data(with start indication). The AND circuit 133′ outputs a “1” in the casewhere the CAM 13 f outputs a “0” indicating the unused state, thevalidity indication a “1” indicating the presence of a valid cell and acomparator 13 i indicates that the up-down counter 13 h is not more thanthe threshold value.

[0143] In the process, the unused address FIFO 13 g is caused togenerate an address, and the PVC is registered in the same address onthe CAM 13 f, so that the up-down counter 13 h is counted up. Also, theoutput “1” of the AND circuit 133′ causes the selector 13 e toselectively output the input cell through the OR circuit 13 c′ and theAND circuit 13 d. This operation permits PVC registration at the time ofarrival of the leading cell of the burst data.

[0144] In the case where an input cell is the leading cell and the valueon the up-down counter 13 h exceeds the threshold value, the AND circuit133′ outputs a “0”. In this case, the PVC is not registered in the CAM13 f and the input cell selection instruction is not issued by theoutput of the OR circuit 13 c′.

[0145] This operation indicates that the burst data that has newlyarrived is not admitted if a predetermined number of other burst dataalready occupy the output line at the time of arrival of the leadingcell of the newly-arriving burst data, and therefore the PVCregistration operation cannot be performed.

[0146] Assuming that an input cell is the last cell (with the endindication). In the case where the validity indication is a “1”indicating the presence of a valid cell and the CAM 13 f outputs a “1”indicating that the PVC is in registration, the AND circuit 134′ outputsa In the process, the corresponding PVC on the CAM 13 f is cancelled,and the address of the record that has so far registered the PVC isstored in the unused address FIFO 13 g as an idle address, so that thevalue on the up-down counter 13 h is counted down.

[0147] As a consequence, the registered PVC of the burst data that hasbeen admitted is canceled, and registration becomes possible for newburst data that arrive subsequently.

[0148] Assuming that the up-down counter is configured to perform theadd operation by a magnitude according to the bandwidth of the burstdata at the time of registration of the identification information ofthe admitted burst data and performs the subtract operation by amagnitude according to the bandwidth of the burst data-at the time ofcancelling the registration of the identification information. Anappropriate admission control becomes possible not exceeding thebandwidth of the output queue for a plurality of burst data havingdifferent bandwidths.

[0149] In this case, it is necessary to acquire bandwidth informationfor each burst data. This can be realized by preparing a tableindicating the bandwidth values for each PVC or by adding informationindicating the bandwidth to the leading cell of the burst data by meansof the line interfaces 2-1 to 2-N or the cellgenerating terminalequipment.

[0150]FIG. 11 is a diagram showing the line interfaces 2-1 to 2-N of theATM switching system of FIG. 1 according to an embodiment.

[0151] The cell input from the line L1 made of an optical fiber, forexample, is converted into an electrical signal by an O/E converter 21,and the transmission frame is terminated by a receiving SDH terminationcircuit 22.

[0152] The cell transmitted by the transmission clock is synchronizedwith the switch-side clock distributed in the ATM switching system at areceiving cell sync circuit 23. The header conversion circuit 24converts the cell header and attaching the required additionalinformation to the header, outputs the cell to line L2 making up aswitch input.

[0153] The cell output to line L5 from the switch is synchronized withthe propagation-side clock from the state synchronized with theswitch-side clock at the transmission-side cell sync circuit 27. Atransmission-side SDH termination circuit 26 places the cell on thetransmission frame, and the E/O converter 25 converts the electricalsignal into an optical signal.

[0154]FIG. 12 is a diagram showing the header conversion circuit 24 ofFIG. 11 according to an 5 embodiment.

[0155] The cell input to the header conversion circuit 24 is separatedinto the data section and the header section by a separator 241, andfurther separated into the VPI/VCI, end indication and other fields bythe header analysis circuit 242.

[0156] Generally, in the AAL5 (ATM Adaptation Layer Type 5), the endindication is attached and used indicating the last cell of the burstdata.

[0157] The header conversion table 243, upon application thereto of theVPI/VCI output from the header analysis circuit 242, outputs a newVPI/VCI together with the validity indication, the output queue number,the type of PVC or SVC and the PVC value. The contents of the headerconversion table 243 are rewritten by the controller 3 through thecontrol bus L0.

[0158] The used/unused table 245 is a table for holding the informationas to whether the output line is occupied or not by the burst data foreach queue according to the PVC.

[0159] Assuming that the validity indication signal is a “1” indicatinga valid cell and the PVC/SVC type signal is a “0” indicating PVC mode.In the case where the information output from the used/unused table 245is a “1” indicating the unused state, this output is applied as a startindication to the selector 24 a, while at the same time causing theoutput value of the OR circuit 248 to be written in the record area inthe used/unused table 245 corresponding to the queue number and the PVCof an arriving cell through the OR circuit 246 and the AND circuit 247.

[0160] In this case, the output value of the OR circuit 248 is a “0”indicating the used state unless the end indication is a “1”. In thewrite operation, therefore, information indicating the used state is setin the used/unused table 245. The header of the leading cell of theburst data has attached thereto a bit pattern indicating the startindication.

[0161] Assuming that the end indication representing the last cell isoutput from the header analysis circuit 242 when the validity indicationis a “1” indicating a valid cell and the PVC/SVC type is a “0”indicating PVC mode. The output value of the OR circuit 248 is writtenin the record area of the used/unused table 245 corresponding to thequeue number and the PVC of the arriving cell through the OR circuit 246and the AND circuit 247. In the process, the output value of the ORcircuit 248 is a “1” indicating the unused state, so that theinformation registered in the used/unused table 245 is cancelled.

[0162] A timer 244 is provided for invoking the end indication forciblyagainst cell admission of given burst data and cancelling the PVCregistration in the case where the particular burst data occupies aqueue for longer than a predetermined length of time unfairlyinterfering with the admission of other burst data.

[0163] With the arrival of the leading cell of burst data, the startindication (unused indication) is output from the used/unused table anda value corresponding to the queue number and the VPI/VCI is reset inthe timer 244. The timer 244 updates the timer value with the progressof time and when a predetermined value is exceeded, outputs a “1” to theOR circuit 249, thereby causing the OR circuit 249 to output a controlsignal “1” indicating the end indication.

[0164] The selector 24 a selects the validity indication, the startindication, the end indication, the queue number, the VPI/VCI, otherpart or data of the header as required. A cell format for the switch isthus constructed and output.

[0165] The header conversion circuit 24 shown above adds the startindication to the leading cell of the burst data and at the same timehas the function of terminating the cell transfer operation forciblyagainst the burst data occupying a queue for a long time.

[0166] As obvious from the foregoing embodiments, according to thisinvention, availability of a bandwidth room is checked for each outputqueue of the ATM switch to pass a given burst data at the time ofarrival of the leading cell of the particular burst data. In the casewhere the bandwidth has a room, the burst data is admitted, while in thecase where the bandwidth has no room, the cells of the burst data areall discarded. As a result, even when a plurality of burst dataexceeding the limit of bandwidth arrive at a specific output line of theATM switch in temporally overlapped fashion, all the cells of the burstdata not admitted are discarded, while the cells of the burst data forwhich the bandwidth has been secured are positively transferred withoutbeing discarded due to buffer overflow.

1. In an ATM switching system including a plurality of input lines and aplurality of output lines, a cell control method for transferringfixed-length packets (cells) input from each input line to an outputline specified according to the header information of the respectivecells, said method comprising the steps of: deciding whether new burstdata is to be Admitted or not in accordance with the amount of otherburst data admitted to one of the output lines to which the leading cellof the new burst data is to be output when the leading cell of said newburst data arrives at the switching system; and admitting only thesubsequent cells of at least one specified burst data that have beenadmitted at the time of arrival of the leading cell thereofrespectively, said burst data being included in a plurality of burstdata and directed to the same output line in temporally overlappedfashion, the cells of the remaining burst data being discarded.
 2. Acell control method according to claim 1 , further comprising the stepsof: registering part of the header information of the leading cell ofthe burst data admitted for transfer to an output line as identificationinformation of the data at the time of arrival of said leading cell ofsaid burst data; and deciding whether the subsequently-arriving cells ofburst data are to be admitted or discarded according to whether theheader of said cells contains the burst identification information inregistration.
 3. A cell control method according to claim 2 , furthercomprising the step of: storing the bandwidth utilization rate for eachoutput line and deciding whether given burst data is to be admittedaccording to the bandwidth utilization fate of the output line to whichthe leading cell of the particular burst data is to be output at thetime of arrival of said leading cell.
 4. A cell control method accordingto claim 2 , further comprising the step of: at least a part of selectedone of the VCI (Virtual Channel Identifier), the VPI (Virtual PathIdentifier) and a combined value of VCI and VPI contained in the headerof the leading cell of burst data is stored as information foridentifying burst data to be admitted.
 5. A cell control methodaccording to claim 3 , further comprising the step of: at least a partof selected one of the VCI (Virtual Channel Identifier), the VPI(Virtual Path Identifier) and a combined value of VCI and VPI containedin the header of the leading cell of burst data is stored as informationfor identifying burst data to be admitted.
 6. An ATM switching systemcomprising a plurality of input lines and a plurality of output linesfor transferring fixed-length packets (cells) input from each input lineto an output line specified in accordance with the header information ofthe respective cells, comprising: buffer memory means for forming anoutput queue of cells corresponding to each output line; register meansfor storing identification information of the burst data admitted foreach output queue; and control means for deciding whether the outputqueue in which the leading cell of burst data is to be accumulatedsatisfies a predetermined condition when said leading cell is inputthereto, and when the predetermined condition is satisfied, accumulatingsaid leading cell in said output queue, storing at least part of theheader information of said leading cell in said register means, saidleading cell being discarded with the subsequently-arriving non-leadingcells being discarded or accumulated in said output queue according tothe result of comparison between the header information of said cellsand the information stored in said register means when saidpredetermined condition is not-.satisfied.
 7. An ATM switching systemaccording to claim 6 , wherein said control means deletes theinformation corresponding to the header information of the last cell ofburst data from said register when said last cell arrives.
 8. An ATMswitching system according to claim 6 , wherein said control meansdecides the manner in which the leading cell of given burst data isprocessed and whether information storage in said register means isrequired in accordance with whether the output queue for accumulatingsaid cells is utilized for storing the cells of other burst data whenthe leading cell of said ‘given burst data is input.
 9. An ATM switchingsystem according to claim 7 , wherein said control means decides themanner in which the leading cell of given burst data is processed andinformation storage in said register means are required in accordancewith whether the output queue for accumulating said cells is utilizedfor storing the cells of other burst data when the leading cell of saidparticular burst data is input.
 10. An ATM switching system according toclaim 6 , wherein said buffer memory means forms a plurality of outputqueues for at least one output line, and when the leading cell of burstdata to be sent out to any of said output lines is input thereto, saidcontrol means selects an output queue not used for storing the cells ofother burst cells, processes said leading cell appropriately andregisters the information in said register means.
 11. An ATM switchingsystem comprising a plurality of input highways and a plurality ofoutput highways for distributing the fixed-length packets (cells) inputfrom said input highways among the output highways in accordance withthe header information of the respective cells, said system furthercomprising: buffer memory means for forming at least one cell outputqueue for each output highway; multiplexer means for converting theparallel cells arriving from said input highways into a serial stream ofcells; and control means for performing the operation of writing saidcells output from said multiplexer means into said buffer memory meansand the operation of reading the cells from said buffer memory means;and demultiplexer means for distributing the cells read from said buffermemory means among said output highways: wherein said control meansincludes first register means for indicating the used or unused state ofburst data for each output queue and second register means for storingthe identification information of the burst data in use for each outputqueue; wherein in the case where the first register means correspondingto the output queue for accumulating the newly-arriving leading cell ofburst data is occupied by other burst data at the time of arrival ofsaid leading cell, said leading cell is discarded, while in the casewhere said first register means indicates the unused state, the firstregister means is rewritten as a used state, the identificationinformation of said burst data is registered in the corresponding secondregister means, and said leading cell is accumulated in the output queuein said buffer memory means; and the header information of the arrivingcells other than the leading cell of the burst data is compared with theburst data identification information stored in said second registercorresponding to the output queue for accumulating said cells, and saidcells are discarded or accumulated in the output queue in accordancewith the result of comparison.
 12. An ATM switching system according toclaim 11 , wherein in the case where said accumulated cell is the lastcell of burst data, said control means rewrites the first register meansas a unused state and deletes the identification information of thesecond register at the same time.
 13. An ATM switching system accordingto claim 11 , wherein said control means discards or accumulates thecells other than the leading cell of burst data in the output queue ofthe buffer memory in accordance with the state of the first registermeans corresponding to the output queue for accumulating said cell andthe correspondence between the burst data identification informationstored in the second register and the header information of said cell atthe time of arrival of said cells, said first register means beingrewritten as an unused state in the case where the accumulated cell isthe last cell of the burst data.
 14. In an ATM switching systemincluding a plurality of input lines and a plurality of output lines fortransferring fixed-length packets (cells) from each input line to anoutput line specified in accordance with the header information of therespective cells, a cell control method comprising the steps of:deciding whether a new burst data in a specified switching mode of theswitching system is to be admitted or not in accordance with the amountof other burst data in said specific switching mode which have beenadmitted for transmission to one of said output lines, when the leadingcell of said new burst data arrives; and admitting only the cells of oneor a plurality of burst data that have been admitted at the time ofarrival of the leading cells thereof in the case where a plurality ofburst data in the specific switching mode directed to the same outputline from a plurality of different input lines arrive in temporallyoverlapped fashion, and discarding the cells of the other burst data.15. A cell control method according to claim 14 , further comprising thestep of admitting the cells of the data other than the burst data insaid specific switching mode to the switching system and outputting saidcells to the output line specified according to the header informationof the respective cells.
 16. A cell control method according to claim 15, further comprising the steps of: registering a part of the headerinformation of the leading cell of burst data admitted to the outputline as the information for identifying the admitted burst data at thetime of arrival of the leading cell of the burst data in said specifiedswitching mode, and deciding whether each of the subsequently arrivingcell is to be admitted or discarded according to whether the header ofeach of said subsequently arriving cells of the burst data in saidspecified switching mode contains said burst identification informationin registration.
 17. A cell control method according to claim 15 ,further comprising the step of storing the bandwidth utilization rate ofeach output line and deciding whether a given burst data is to beadmitted or not in accordance with the bandwidth utilization rate ofsaid output line at the time of arrival of the leading cell of the burstdata to be output to said output line.
 18. A cell control methodaccording to claim 15 , further comprising the step of storing selectedone of the VCI (Virtual Channel Identifier), the VPI (Virtual PathIdentifier) and at least a part of a combined value of the VCI and VPIcontained in the header of the leading cell of the burst data as theinformation for identifying said admitted burst data.